The present invention relates to testing of integrated circuits with automated test equipment.
Integrated Circuits (IC) generally need to be tested to assure proper operation. This—in particular—is required during IC development and manufacturing. In the latter case, the ICs are usually tested before final application. During test, the IC, as a device under test (DUT), is exposed to various types of stimulus signals, and its responses are measured, processed and usually compared to an expected response of a good device. Automated test equipment (ATE) usually performs these tasks according to a device-specific test program.
During test, each pin of the DUT that is relevant for this test is connected to the ATE's pin electronic. There are generally two types of ATEs: one type with centralized resources and another type with decentralized resources based on a per-pin architecture. In the latter case, the resources on the per-pin basis further comprise some central resources, in particular for centrally controlling the sequence and period of applied test stimulus vectors. The per-pin architecture generally enables high performance and scalability at acceptable costs. Examples for ATE with per-pin architecture are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A886214, EP-A-882991, U.S. Pat. Nos. 5,499,248, 5,453,995.
The semiconductor industry is characterized by an ever-increasing integration of capabilities on a single IC. In the last years, ICs can be designed encompassing virtually all functions that constitute a complete (end-user) system. Such devices are generally called systems on a chip (SOC). A typical SOC integrates a set of analogous, digital, or memory DUT-cores that are used in multiple designs in order to gain design productivity. The term ‘DUT-core’ as used herein shall generally represent an architectural component within an IC (as DUT) that is characterized by an interface that is specified in terms of a set of input and output signals, signal timing conditions and a behavioral model (much like an independent device). Increasingly, SOCs are designed hierarchically, i.e. fully designed DUT-cores are integrated into the SOC.
FIG. 1 shows an example of an SOC with internal and peripheral DUT-cores. In this example, the SOC 10 comprises, as internal DUT-cores 15, a Random Access Memory (RAM) 20, a Read-Only Memory (ROM) 30, a Micro Processor Unit (MPU) 40, a Digital Signal Processor (DSP) 50, and an Graphics Processor Unit (GPU) 60. As peripheral DUT-cores, the SOC 10 in this example comprises a Local Area Network (LAN) module 70, a flat panel interface 80, an audio block 90, a Dynamic Random Access Memory (DRAM) 100, an Universal Serial Bus (USB) 110, a High-Speed Serial Interface (HSS) 120, and a scalability bus 130 (e.g. an Advanced Graphics ATE-port—AGP). The SOC 10 in the example of FIG. 1 integrates all major functions and interfaces of a personal computer (PC) and could be applied for a highly-integrated notebook.
DUTs become increasingly complex internally, while the bandwidth (as the product of the number of signal pins and the data rate) of a DUT-interface does not increase correspondingly. The DUT-interface refers to all signal pins of the DUT that are used for communication with the environment of the DUT and specifically for testing the DUT. Since the test stimulus and response data have to flow through the DUT interface, the testing time and thus the related testing cost for testing SOCs become excessive.